In the area of electronic components, it is highly desirable to provide integrated circuits which consume a minimum of electric power and which function at high speeds. CMOS integrated circuits in general meet these requirements.
It is more specifically desired to provide a CMOS circuit, which can be implemented, for example, as part of a monolithic integrated circuit, having CMOS input buffers whose performance is significantly improved in several ways. First, it is desired that a CMOS input buffer circuit be capable of accepting TTL level signal inputs and translating them into CMOS level signal outputs. Secondly, this must be done without consuming undue electric power. Thirdly, it is desired to provide such CMOS input buffer circuits with performance that is relatively immune to variations in manufacturing process parameters and to power supply changes. Fourthly, it is desired to provide a CMOS input buffer circuit which operates at a relatively higher speed than known CMOS input buffer circuits.
A known CMOS inverting input buffer circuit is shown in FIG. 2, comprising input pad 70, a pair of N-channel devices 72 and 76, and a P-channel device 74. The prior art input buffer circuit is capable of translating a TTL-level input (ranging from a "low" input of 0.8 volts to a "high" input of 2.0 volts) into CMOS-level outputs, but it has a relatively high current consumption.
In the prior art circuit shown in FIG. 2, the function of N-channel device 72 is to drop the supply voltage V.sub.DD by one N-channel threshold, so that the gate-to-source potential drop across P-channel device 74 is minimized in order to minimize the current flowing through device 74 when the input level on pad 70 is "high". The supply voltage V.sub.DD is typically 5.0 volts .+-.0.25 volts.
P-channel device 74 and N-channel device 76 are ratioed (i.e., device 76 is given a higher current channel W/L ratio) to try to reduce the power consumption at the higher levels of the supply voltage V.sub.DD, and to allow device 76 to sink the current flowing through devices 72 and 74 when the input is "high".
A disadvantage of the known CMOS input buffer circuit is that it is always drawing current when the input has a "high" level on input pad 70, so that its level of DC power consumption, while relatively low for many applications, is too high for other applications where power must be strictly conserved. For example, where it is used to implement a relatively large number of tri-stated input/output buffers, the power consumption is quite large.